Synopsys design compiler
If you used the Synopsys library file without making any changes, you should be able to use the following file without modification. The netlist is not yet complete, however, as we need to add module descriptions for each of the devices as well. It describes the circuit as a network of devices with names and pins as specified by the Synopsys library. The resulting verilog (or VHDL) file is a gate-level netlist of your design. Now close Synopsys Design Vision by selecting File->Exit. output: fsm_syn.v) and select verilog (or VHDL) as the file format from the drop-down menu. Specify the filename as your original verilog (or VHDL) file with the addition of _syn.v (i.e.: original: fsm.v. To create a verilog (or VHDL) mapped netlist for your design, select File->Save As again. So my suggestion is: If you compile without ungroup and get the cells required in the project description AND all the cells are from the library, that's fine. That's why you get more cell count with ungroup. While the cells in right result are all from our library. The left result has some cells that are not from the library we use, which is not allowed. The above picture shows the cell reports from a compile result without checking the ungroup option (left) v.s. This can obtain area benefits by possibly combining redundant logic. If we choose to ungroup, Design Vision will take all of the logic within the module and combine it with the logic at other levels of the design. Ungrouping removes (or collapses) the level of hierarchy of the identified subdesign and merges the subdesign with the surrounding logic. Removing a level of hierarchy is called ungrouping. The grouped cells are replaced by a new instance (cell) that references the new module. The group command groups cells (instances) or related components in the design into a new module, creating a new level of hierarchy.
#Synopsys design compiler code#
So your code must not infer latches and should be written in a synchronous fashion. Your mapped netlist can only use Flip flops, instead of latches. Since we will design a positive/negative edge triggered Flip flop, and no latch. ) will infer latches and should be avoided ! If there are some instances like **SEQGEN** or **FFGEN** from the GTECH library then your mapping is incorrect.Īlways (sginal. Make sure all the instance are mapped from the library. You will see the list of cells and total number of them. To check your cell number, select Desing -> Report Cells and then OK. You can check options Ungroup all and Auto ungroup for best results to flatten your verilog netlist. To do that select Design->Compile Design from the menu bar and click OK in the window that pops up. Note that you have just read in your design, You have not compiled or mapped it into digital gates yet.
In the Read File dialog box, select your verilog file and click OK.įile -> Analyze and then, click Add, and add your file.
Open your design by selecting File->Read from the menu bar.
If you store library.db at other location, you can not use default setting, set library location as following.